In accordance with speed-up, increase in capacity, and reduction in size of a computer or an electronic device, an operating speed of a serializer/de-serializer (SerDes) by which semiconductor integrated circuits (LSIs) and the like are communicated with a serial signal, is increasing. As illustrated in an example in FIG. 8, a semiconductor integrated circuit (LSI) 110 on a transmitting side (Tx) performs, by a serializer 112, parallel-to-serial conversion on parallel data output from an internal circuit 111 to convert the parallel data to serial data, and transmits the serial data. The serializer 112 converts, with the use of a multiplexer 113, the parallel data into the serial data by using a clock output from a phase locked loop (PLL) circuit 114, and transmits the serial data via an equalizer 115.
A semiconductor integrated circuit (LSI) 120 on a receiving side (Rx) performs, by a de-serializer 122, serial-to-parallel conversion on the serial data received via a transmission path (communication channel) 130 to return the serial data to the parallel data, and supplies the parallel data to an internal circuit 121. The de-serializer 122 converts, with the use of a demultiplexer 124, the serial data received via an equalizer 123 into the parallel data by using a clock output from a PLL circuit 126 and having a phase and the like adjusted by a clock data recovery (CDR) circuit 125, and outputs the parallel data.
In communication using a serial signal, a CDR system in which a clock is embedded, on a transmitting side, in a data signal to be transmitted, and the embedded clock is reproduced, on a receiving side, from the received data signal, is a useful technique. A CDR circuit which reproduces a clock and data from a received data signal, is a negative-feedback circuit which controls to make a phase of a clock follow the received data. In order to realize an appropriate operation in the receiving-side circuit, there is a need to control appropriately a negative-feedback loop gain in the CDR circuit. As one of requests for a serializer/de-serializer, the serializer/de-serializer is requested to quickly lock a CDR circuit (to quickly put the CDR circuit in a stable).
There is proposed a PLL circuit in which determination is made whether or not the PLL circuit is locked in operation, and a gain of the PLL circuit is automatically controlled based on a result of the determination (refer to Patent Document 1, for example). The proposed PLL circuit performs the automatic control in a manner that the gain is reduced when the PLL circuit is locked, and the gain is increased when the PLL circuit is not locked, based on the result of the determination, to thereby realize reduction in capture time and improvement of error rate.
[Patent Document 1] Japanese Laid-open Patent Publication No. 2010-41639
In a CDR circuit, in a case where a negative-feedback loop gain is too small, it takes a long time until when the circuit is locked. On the other hand, in a case where the negative-feedback loop gain is too large, a frequency of occurrence of error when the circuit is locked is increased, resulting in that reliability of data is decreased. A loop gain in a conventional CDR circuit is set to a fixed value previously obtained through calculation, in order to realize an appropriate loop characteristics. If the fixed value is too large, oscillation occurs or an error frequency increases when the circuit is locked, and thus the fixed value is restricted by the loop gain in the locked state, so that it is difficult to increase the loop gain to reduce a time until when the circuit is locked in the CDR circuit of a reception circuit.